1. Field of the Invention
The present invention relates to an art for interfacing a signal between integrated circuits. More particularly, this invention relates to an interface circuit that uses a current signal as a signal to be interfaced between integrated circuits and thus permits a high-speed operation.
2. Description of the Related Art
With an increase in the number of steps of CMOS processing, internal circuit elements of a CMOS integrated circuit (IC) have come to be able to operate at several hundreds of megahertz (MHz). However, an interface circuit provided as an input/output circuit cannot operate at a high speed. This hinders high-speed operation of an entire CMOS IC.
An interface circuit for a CMOS IC is therefore requested to operate at a high speed so that a function realized with the CMOS IC can cope with quick operations of the internal circuit elements.
Conventionally, a CMOS IC has had a lower operation speed than a bipolar IC or a gallium arsenide (GaAs) IC. In recent years, with an increase in the number of steps of CMOS processing, circuit elements of an IC have come to be able to operate at several hundreds of megahertz.
However, an interface circuit cannot input or output a high-speed signal due to a parasitic capacitance in a protective circuit usually included in an input or output unit in a CMOS IC and designed to prevent electrostatic destruction (ESD) or in a bonding pad.
FIG. 1a shows circuit elements of a CMOS interface circuit in accordance with an example of a prior art. FIG. 1b shows waves of an input/output signal for the circuit.
In FIG. 1a, IC1 denotes a CMOS IC on a transmitting side. 101 denotes an output buffer incorporated in IC1. IC2 denotes a CMOS IC on a receiving side. 102 denotes an input buffer incorporated in IC2. L denotes a line on a printed circuit board for linking IC1 and IC2. 103 denotes a counter-ESD protective circuit connected to an input terminal of IC2 over the line L on the printed circuit board. The line L and the counter-ESD protective circuit 103 possess a parasitic capacitance C of about 10 pF as a whole, which is a cause of preventing input or output of a high-speed signal.
A conventional mainstream of a high-speed interface circuit is a bipolar ECL interface. Using an ECL interface, a CMOS IC can operate as high a speed as, for example, about 100 MHz. However, the ECL interface has a drawback of a large power consumption.
An interface circuit in an IC serving as a memory or a microprocessor is sometimes required to provide interface for 32-bit parallel operation. In this case, the power consumption of the interface circuit in an input or output unit is large, causing a chip temperature to rise and reliability to degrade. This disables high-speed operation.
On the other hand, an existing IC serving as a microprocessor or the like typically operates at a supply voltage of +5 V. A future trend heads toward operation at a low voltage (for example, +3 V). In this case, it is economic to use a single power supply for all circuit elements in a printed circuit board. Consequently, there arises a demand for an interface circuit capable of operating at a lower voltage.
As mentioned above, when an interface circuit for a CMOS IC is requested to operate at a high speed, an ECL interface must be employed. This leads to a large power consumption and a high price. In contrast, when a highly economical CMOS processing method is adopted, high-speed operation cannot be realized.
In line with a trend toward operation at a lower voltage, an interface circuit capable of operating at a low voltage is needed. Known prior arts have failed to implement such an interface circuit.